DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
FPGA-specific synthesis of loop-nests with pipelined computational cores
Microprocessors & Microsystems
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Model Based Design tools based around Simulink from The MathWorks are a popular technology for the creation of streaming DSP designs for FPGAs, since they offer the promise of rapid design exploration through immediate quantitative feedback of algorithm performance. Current tools typically use a library of components that reflect an explicit representation of the underlying FPGA device features. This is undesirable since the designer is forced to mix implementation and architecture, and leads to long design cycles and non-portable results. This paper shows that introducing techniques of high level synthesis allows a more elegant design at a higher level of abstraction. This results in fewer components needed for a design which translates into a faster design cycle, more portable designs and fewer defects. Pushbutton clock frequencies of up to 500 MHz are achieved without detailed knowledge of FPGA architectures. Although the capabilities described are embodied in the DSP Builder tool from Altera, this paper describes the technology involved rather than the details of the tools. Four major technologies are described: a latency-insensitive system representation, the module level internal representation with associated transformations, hardware retiming, and lastly a FIR filter design tool layered on top.