Logic synthesis
Principles of digital design
Introduction to the Scheduling Problem
IEEE Design & Test
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Incorporating DRAM access modes into high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrating variable-latency components into high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We consider the problem of synthesizing circuits (from C to Verilog) that are optimized to handle unpredictable latencies of memory operations. Unpredictable memory latencies can occur due to the use of on chip caches, DRAM memory modules, buffers/queues, or multiport memories. Typically, high-level synthesis compilers assume fixed and known memory latencies, and thus are able to schedule the code’s operations efficiently. The operations in the source code are scheduled into states of a state machine whose states will be synthesized to Verilog. The goal is to minimize scheduling length by maximizing the number of operations (and in particular memory operations) that are executed in parallel at the same state. However, with unpredictable latencies, there can be an exponential number of possible orders in which these parallel memory operations can terminate. Thus, in order to minimize the scheduling, we need a different schedule for any such order. This is not practical, and we show a technique of synthesizing a compact state machine that schedules only a small subset of these possible termination orders. Our results show that this compact state machine can improve the execution time compared to a regular scheduling that waits for the termination of all the active memory references in every state.