A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
GALS networks on chip: a new solution for asynchronous delay-insensitive links
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
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Many research activities in the area of Network on Chip (NoC) architectures have been performed. The results achieved up to now are quite attractive but often are not directly applicable because of technological reasons or implementation difficulty. In this paper an industrial experience is presented by introducing the approach followed to support the transition from the traditional interconnects to the NoC architectures. The paper mainly focuses on the strategy used to overcome physical issues and particularly the difficulty to perform system synchronization.