Relieving physical issues in new NoC-based SoCs
Proceedings of the 2nd international conference on Nano-Networks
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
The increasing complexity of System on Chip (SoC) architectures and the physical issues due to the CMOS technology scaling, led to explore new solutions to build effective on-chip interconnection and communication infrastructures. Network on Chip (NoC) paradigm has been proposed as architectural solution mainly for overcoming scalability and flexibility limitations. However, advanced techniques to mitigate wire-delay effects have to be employed to reduce the impact of physical issues. Globally Asynchronous Locally Synchronous (GALS) paradigm has been selected to this purpose as solution to implement the NoC physical layer, and many different approaches to design GALS-based NoC can be used. In this paper a full-duplex mesochronous link architecture, for which a patent has been submitted, is proposed to effectively implement the GALS paradigm in the STNoCTM system. Such a link, exploiting the service provided by the newest mesochronous physical layer known as SKIL, effectively implements the mesochronous communication at data-link layer and enables to overcome some important issues of the previous mesochronous solutions.