GALS networks on chip: a new solution for asynchronous delay-insensitive links
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
| Hi-index | 0.00 |
The composability dimension of asynchronous circuits is extended to incorporate delay-insensitivity, area utilisation and layout complexity. The disadvantages of conventional delay-insensitive data paths are established, and an alternative solution based on tri-state buffers is presented. The solution maintains the same delay-insensitivity, while achieving a significant reduction in circuit area utilisation and layout complexity of the data path.