A generic packet router IP for multi-processors network-on-chip

Authors:
Loïc Siéler;Lionel Damez;Benoit Ballet;Alexis Landrault;Jean-Pierre Dérutin
Affiliations:
Institut Pascal - LASMEA, UMR, CNRS, Clermont-Ferrand, France;Institut Pascal - LASMEA, UMR, CNRS, Clermont-Ferrand, France;Institut Pascal - LASMEA, UMR, CNRS, Clermont-Ferrand, France;Institut Pascal - LASMEA, UMR, CNRS, Clermont-Ferrand, France;Institut Pascal - LASMEA, UMR, CNRS, Clermont-Ferrand, France
Venue:
Proceedings of the 8th FPGAWorld Conference
Year:
2011

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Abstract

In this paper, a generic IP is proposed to ensure communication for a Multi-Processors System on Chip (MPSoC) architecture. It is based on a specific hardware router and its associated Direct Memory Access (DMA) module. This scalable IP makes the instantiation easier and faster in MPSoC systems based on hypercube topology. Besides the hardware description, this work also presents the software layer and the communication functions developed to help the parallel programming based on functional skeletons. Implementation results are given regarding processing time, area and processor number on a Virtex 6 Xilinx FPGA target.