The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
The feasibility of on-chip interconnection using antennas
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
RF interconnects for communications on-chip
Proceedings of the 2008 international symposium on Physical design
Dynamically configurable bus topologies for high-performance on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power reduction of CMP communication networks via RF-interconnects
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
IEEE Transactions on Computers
A Novel Technique Enabling the Realisation of 60 GHz Body Area Networks
BSN '12 Proceedings of the 2012 Ninth International Conference on Wearable and Implantable Body Sensor Networks
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip
IEEE Transactions on Parallel and Distributed Systems
ORION 2.0: A Power-Area Simulator for Interconnection Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing power supply noise through harmonic mappings in networks-on-chip
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Network-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and satisfy different demands in terms of high performance and economical interconnect implementation. However, merely metal based interconnect pursuit offers limited scalability with the relentless technology scaling. To meet the scalability demand, this paper proposes a new hybrid interconnect fabric empowered by metal interconnect NoC and Zenneck surface Waves Interconnect (SWI) technology. Our initial results show a considerable power reduction (9 to 17%) and performance improvement (35%) of the proposed hybrid architecture compared to regular NoC. These results are achieved over relatively small hardware and area overhead (2.29% of die). This paper explores promising potentials of SWI for future System-on-Chip (SoC) global communication.