Characterizing computer performance with a single number
Communications of the ACM
The use of the L-curve in the regularization of discrete ill-posed problems
SIAM Journal on Scientific Computing
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Rivet: a flexible environment for computer systems visualization
ACM SIGGRAPH Computer Graphics
Exploiting thread-level parallelism on simultaneous multithreaded processors
Exploiting thread-level parallelism on simultaneous multithreaded processors
Using visualization to understand the behavior of computer systems
Using visualization to understand the behavior of computer systems
High level cache simulation for heterogeneous multiprocessors
Proceedings of the 41st annual Design Automation Conference
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
Proceedings of the 31st annual international symposium on Computer architecture
PerfExplorer: A Performance Data Mining Framework For Large-Scale Parallel Computing
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Core architecture optimization for heterogeneous chip multiprocessors
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Interrupt modeling for efficient high-level scheduler design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Nonlinear Mapping for Data Structure Analysis
IEEE Transactions on Computers
Analyzing memory access intensity in parallel programs on multicore
Proceedings of the 22nd annual international conference on Supercomputing
Amdahl's Law in the Multicore Era
Computer
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
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Chip Heterogeneous Multiprocessors (CHMs) are increasingly used to execute multichannel, heterogeneous workloads, often in the service of single users. Multichannel inputs can be processed at different rates and in a variety of combinations. We show that performance evaluation of the CHMs that process multichannel workloads requires a new performance metric, capacity, which we introduce in this paper. We show how capacity is a successor to throughput, through an automobile production analogy. We include experimental results to illustrate the form and usefulness of the new metric as well as contrast it with Pareto optimization.