Capacity metric for chip heterogeneous multiprocessors
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Single-chip systems, featuring multiple heterogeneous processors and a variety of communication and memory architectures, have emerged to satisfy the demand for networking, handheld computing, and other custom devices. When simulated at cycle-accurate level, these system models are slow to build and execute, severely limiting the number of design iterations that can be considered. A key challenge in raising the simulation level above the clock cycle is an effective method for estimating contention for shared resources such as memories and busses. This paper introduces a new level of design called the Stochastic Contention Level (SCL). Instead of considering shared resource accesses at the clock cycle granularity, SCL simulations operate on blocks that are thousands to millions of clock cycles long, stochastically capturing contention for shared resources via sampled access attributes, while still retaining an event-based simulation framework. The SCL approach results in speedups of 40{\times} over cycle-accurate simulation, with average simulation errors of less than one percent with 95 percent confidence intervals of about \pm 3{\rm percent}, providing a unique combination of simulation capabilities, performance, and accuracy. This significant increase in simulation performance enables the system designers to explore more of the design space than possible with traditional simulation approaches.