LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Performance analysis of different arbitration algorithms of the AMBA AHB bus
Proceedings of the 41st annual Design Automation Conference
ACM Transactions on Embedded Computing Systems (TECS)
Hi-index | 0.00 |
In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms. We propose an arbitration algorithm, RT_lottery, which is designed to meet both hard real-time and bandwidth requirements. For fast evaluation and exploration, we use high abstract-level models in our system simulation environment to generate parameters for our configurable arbiter. The experimental results show that RT_lottery can meet all hard real-time requirements and perform very well in bandwidth allocation. The results also show that RT_lottery outperforms several commonly-used arbitration algorithms today.