The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Towards efficient design space exploration of heterogeneous embedded media systems
Embedded processor design challenges
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Evolutionary Algorithms for Solving Multi-Objective Problems (Genetic and Evolutionary Computation)
Evolutionary Algorithms for Solving Multi-Objective Problems (Genetic and Evolutionary Computation)
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem
Software—Practice & Experience
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Network on Chip (NoC) is a new paradigm for design core-based System on Chip (SoC). It is expected to provide higher computation power due to its higher clock frequencies and parallel execution of processes. This paper addresses the problem of topological mapping of Intellectual Properties (IPs) on the tile of a mesh-based NoC. As the stated problem is NPhard in nature, we propose a heuristic technique based on multiobjective Genetic Algorithm (GA) to obtain an optimal approximation of the pereto-optimal front. The evaluation performed on three randomly generated benchmarks and a real application (a M-JPEG encoder) to conform the efficiency, accuracy and scalability of the proposed approach. Our proposed approach saves up to 15 20% of energy and more than 15% of bandwidth requirement compared with the existing approaches.