SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Communication Architecture Synthesis of Cascaded Bus Matrix
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A methodology for constraint-driven synthesis of on-chip communications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Application-Specific Design Methodology for On-Chip Crossbar Generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width) with their implementation costs such as delay, area, and power. More precisely, they characterize the switches by synthesizing them with a common design objective (e.g. minimizing area) and common design constraints for a given gate-level design library. The implementation costs are used in evaluating the topologies throughout the topology synthesis. The major drawback of single switch library approach is that it forces the topology synthesis methods to search the best topology with the assumption that all the switches comprising a topology will be implemented (synthesized) with a common design objective and common design constraints. Such assumption prevents them from exploring diverse combinations of the switches for a topology from the implementation perspective. To tackle this issue, we propose a topology synthesis method with multiple switch libraries, where the switch libraries are prepared with different design objectives and design constraints. The experimental results show that the power consumption and the area of optimal topologies can be saved by up to 67.1% and 27.2%, respectively, by the proposed method with negligible synthesis time overhead.