Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
3D integration for power-efficient computing
Proceedings of the Conference on Design, Automation and Test in Europe
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
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This paper details the design and implementation of an asynchronous 3D-NoC router using a novel serialization scheme in the vertical directions which targets 3D production oriented processes. A study of the router cost has been conducted for medium and high density TSVs on 65nm and 32nm nodes. A router integrating the serial link has been implemented in 65nm using medium density TSVs. The serial link provides a throughput of 16 Gb/s for an area gain of 57%, and an additional cost of one NoC routing hop in latency and in energy.