Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Power distribution paths in 3-D ICS
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Proceedings of the 11th international workshop on System level interconnect prediction
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The design implications of two distinct through silicon via (TSV) fabrication methods (via-first and via-last) have been investigated for power delivery in a 3D system. Different geometry, connectivity, and filling materials have been considered to develop equivalent electrical models for both via-first and via-last based power distribution networks. Based on these models, a valid design space has been developed where power supply noise is satisfied and physical area overhead is minimized. Under constant power supply noise, a via-last based power network occupies 7.5% less area. However, in addition to causing routing blockages, a via-last based power network exhibits high sensitivity to design parameters due to a high quality factor. Alternatively, a via-first based power network requires a large number of TSVs, but exhibits relatively more predictable behavior due to a lower quality factor (higher damping).