CMOS Photonics for High-Speed Interconnects
IEEE Micro
IBM Journal of Research and Development - POWER5 and packaging
Overview of candidate device technologies for storage-class memory
IBM Journal of Research and Development
Frontiers of information technology
IBM Journal of Research and Development
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols
Journal of Parallel and Distributed Computing
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To satisfy the economic drive for ever more powerful computers to handle scientific and business applications, new technologies are needed to overcome the limitations of current approaches. New memory technologies will address the need for greater amounts of data in close proximity to the processors. Three-dimensional silicon integration will allow more cache and function to be integrated with the processor while allowing more than 1,000 times higher bandwidth communications at low power per channel using local interconnects between Si die layers and between die stacks. Integrated silicon nanophotonics will provide low-power and high-bandwidth optical interconnections between different parts of the system on a chip, board, and rack levels. Highly efficient power delivery and advanced liquid cooling will reduce the electrical demand and facility costs. A combination of these technologies will likely be required to build exascale systems that meet the combined challenges of a practical power constraint on the order of 20 MW with sufficient reliability and at a reasonable cost.