Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Clock tree analysis and signoff is a key step in the design of any high performance chip. Though simple and intutive metrics like skew have been used to track clock tree quality, they are not sufficient for most practical purposes. Ideally, skew distribution obtained using a SSTA (Statististical Static Timing Analysis) on the clock trees can be used. But in most practical cases, the process information assumed by SSTA is not available. As a result, the signoff of clock skew robustness to variation effects is an often difficult problem to solve. In this work, we propose two metrics that can address this issue. These metrics can be used in three important ways. First, they can be used to determine during CTS whether the clock tree is good enough to go through rest of the backend flow or whether more tuning needs to be done to the clock tree. Second, they can be used to isolate any parts of the clock tree that behaves like a hot spot for clock skew across corners. Third, it can be used as a final signoff metric for clock tree to ensure that the tracking of the delays and skews can be expected to be good across all process points. We provide several experimental results fromindustry testcases demonstrating the utility of our metrics.