A multi-resolution approach for line-edge roughness detection
Microelectronic Engineering
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The impact of line edge roughness on the resistivity of copper interconnects in the sub-100 nm range has been calculated. An analytical model has been derived in order to describe the resistivity change. It has been found, that the resistivity is significantly increased compared to interconnect structures with smooth sidewalls for linewidths smaller than 50 nm and peak-to-peak variations of the widths exceeding 30 nm. As root causes of the increase geometrical effects combined with the size-dependent resistivity increase of nanometer-scale interconnects have been identified. Therefore, similar results are expected to apply for other metallization schemes, for example subtractively patterned aluminum.