Giga-hertz rate single slope conversion technique with 512-phase RTWO

Authors:
John Wood;Ahmet Tekin;Adrian Dave;Kenneth Pedrotti
Affiliations:
Multigig Inc., Scotts Valley, USA 95066;Multigig Inc., Scotts Valley, USA 95066 and Department of Electrical and Computer Engineering, University of California, Santa Cruz, USA 95064-1077;Multigig Inc., Scotts Valley, USA 95066;Department of Electrical and Computer Engineering, University of California, Santa Cruz, USA 95064-1077
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2008

Citing 2
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Abstract

In this paper, an 8-bit 1.2 Gsample/s single-slope ADC architecture is presented. The proposed technique utilizes the picosecond-accurate phases of a rotary traveling wave oscillator (RTWO). The proof-of-concept test chip is fabricated in a 0.18-μm CMOS process and occupies 1.3 mm 脳 1.3 mm of die area. Power consumption is 36 mW for the core and 135 mW for on-chip clocks.