An analysis of interconnect delay minimization by low-voltage repeater insertion

Authors:
Rajeevan Chandel;S. Sarkar;R. P. Agarwal
Affiliations:
Department of Electronics & Communication Engineering, National Institute of Technology Hamirpur, Hamirpur 177 005, Himachal Pradesh, India;Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee 247 667, Uttaranchal, India;Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, Roorkee 247 667, Uttaranchal, India
Venue:
Microelectronics Journal
Year:
2007

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Abstract

The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion.