RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
PRIMO: probability interpretation of moments for delay calculation
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
PERI: a technique for extending delay and slew metrics to ramp inputs
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Interconnect Delay and Slew Metrics Using the First Three Moments
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Piece-wise approximations of RLCK circuit responses using moment matching
Proceedings of the 42nd annual Design Automation Conference
Computation of signal threshold crossing times directly from higher order moments
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical modeling of cross-coupling effects in VLSI interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integration, the VLSI Journal
Practical variation-aware interconnect delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Closed-form solution for timing analysis of process variations on SWCNT interconnect
Proceedings of the 11th international workshop on System level interconnect prediction
Interconnect delay and slew metrics using the beta distribution
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we introduce simple metrics for the slew rate of an RC circuit based on the first two circuit moments. We develop two new slew metrics, S2M (slew with 2 moments) and scaled S2M, that provide high accuracy with the advantage of simple closed form expressions. S2M is very accurate for middle and far end nodes but it does not perform as well for near end nodes. Scaled S2M is developed to improve upon S2M for near end nodes and is shown to be highly accurate for near as well as far end nodes. For a large set of nets from an industrial 0.18 μm microprocessor, S2M matches SPICE within 2% on average with 78% of the sinks having less than 1% error. For the same test cases, the average error for scaled S2M is less than 3% with 99.4% of the nodes showing less than 5% error.