A timing-driven module-based chip design flow

Authors:
Fan Mo;Robert K. Brayton
Affiliations:
University of California, Berkeley, CA;University of California, Berkeley, CA
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

Citing 2
Cited 1

Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis
Fishbone: a block-level placement and routing scheme

Proceedings of the 2003 international symposium on Physical design

Budgeting-free hierarchical design method for large scale and high-performance LSIs

Proceedings of the 43rd annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

A Module-Based design flow for digital ICs with hard and soft modules is presented. Versions of the soft modules are implemented with different area/delay characteristics. The versions represent flexibility that can be used in the physical design to meet timing requirements. The flow aims at minimizing the clock cycle of the chip while providing quicker turn-around time. Unreliable wiring estimation is eliminated and costly iterations are reduced resulting in substantial reductions in run time as well as a significant decrease in the clock periods.