Accuracy and fidelity of fast net length estimates
Integration, the VLSI Journal
Prelayout estimation of individual wire lengths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
A force-directed macro-cell placer
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Toward accurate models of achievable routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design methodology and tools for NEC electronics' structured ASIC ISSP
Proceedings of the 2004 international symposium on Physical design
A timing-driven module-based chip design flow
Proceedings of the 41st annual Design Automation Conference
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
Flexible ASIC: shared masking for multiple media processors
Proceedings of the 42nd annual Design Automation Conference
| Hi-index | 0.01 |
A block-level placement and routing scheme called Fishbone is presented. The routing uses a two-layer spine topology. The pin locations are configurable and restricted to certain routing grids in order to ensure full routability and precise predictability. With this scheme, exact net topologies are determined by pin positions only; hence during block placement, net parameters such as wire length (and delay) can be derived directly. The construction of Fishbone nets is much faster than for Steiner trees; this enables the integration of block placement and routing; there is no separate routing stage.