A case study for NoC-based homogeneous MPSoC architectures

  • Authors:
  • Sergio V. Tota;Mario R. Casu;Massimo Ruo Roch;Luca Macchiarulo;Maurizio Zamboni

  • Affiliations:
  • Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy;Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy;Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy;Department of Electrical Engineering, University of Hawaii, Honolulu, HI;Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2009

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Abstract

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processor.