The SP2 high-performance switch
IBM Systems Journal
The SGI Origin: a ccNUMA highly scalable server
Proceedings of the 24th annual international symposium on Computer architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Delay Model for Router Microarchitectures
IEEE Micro
DISHA: a deadlock recovery scheme for fully adaptive routing
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
A Progressive Approach to Handling Message-Dependent Deadlock in Parallel Computer Systems
IEEE Transactions on Parallel and Distributed Systems
Guaranteeing the quality of services in networks on chip
Networks on chip
Integrated shared-memory and message-passing communication in the alewife multiprocessor
Integrated shared-memory and message-passing communication in the alewife multiprocessor
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Router architecture for high-performance NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
NoC Topologies Exploration based on Mapping and Simulation Models
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Flattened Butterfly Topology for On-Chip Networks
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking
User-aware dynamic task allocation in networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Distributed flit-buffer flow control for networks-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Flexible filters: load balancing through backpressure for stream programs
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Virtual channels vs. multiple physical networks: a comparative analysis
Proceedings of the 47th Design Automation Conference
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deadlock prevention in the ÆTHEREAL protocol
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Connection-then-credits (CTC) is a novel end-to-end flow control protocol to handle message-dependent deadlocks in best-effort networks-on-chip (NoC) for embedded multicore systems-on-chip (SoCs). CTC is based on the classic end-to-end credit-based flow control protocol but differs from it because it uses a network interface microarchitecture where a single credit counter and a single input data queue are shared among all possible communications. This architectural simplification reduces the area occupation of the network interfaces and increases their design reuse; for instance, the same network interface can be used to connect a core independently of the number of incoming and outgoing communications. CTC, however, requires a handshake preamble to initialize the credit counter in the sender network interface based on the buffering capacity of the receiver network interface. While this necessarily introduces a latency overhead in the transfer of a message, simulation-based experimental results show that the penalty in performance is limited when large messages need to be transferred, thus, making CTC a valid solution for particular classes of applications such as video stream processing.