An automatic design flow for mapping application onto a 2D mesh NoC architecture

Authors:
Julien Delorme
Affiliations:
INSA/IETR Laboratory, Rennes Cedex, France
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

Complex application specific SoC are often based on the Network-on-Chip (NoC) approach. NoC are under investigation since several years and many architectures have been proposed. Generic NoC are often proposed with their synthesis tool in order to rapidly tailor a solution for a specific application implementation. The optimized mapping of cores on a NoC and the optimized NoC configuration in terms of topology, FIFO and link sizes for instance is a new research area which is investigated deeply now. Validation and evaluation of solutions is often conducted through simulations. Comparisons between proposed optimization approaches is difficult as they use their own evaluative application. Benchmarking is a classical solution to normalize comparisons. We are proposing in this paper a complete design flow which allow to make an automatic Algorithm Architecture Adequation (AAA) onto a NoC architecture. This flow is based on a SystemC model simulation at TLM level. We illustrate these design flow with a benchmark of an 4G radiocommunication application.