Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Journal of Systems Architecture: the EUROMICRO Journal
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling framework for real-time dependable NoC-based systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Network-on-chip-based multiprocessor systems-onchip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel platform involves scheduling the communication on the network-on-chip. This paper presents different scheduling strategies that minimize resource usage by exploiting all scheduling freedom offered by networks-on-chip. Our experiments show that resource-utilization is improved when compared to existing techniques.