Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Introduction to the GiNaC framework for symbolic computation within the C++ programming language
Journal of Symbolic Computation
Introduction to Linear Optimization
Introduction to Linear Optimization
Introduction to Algorithms
Consistency in Dataflow Graphs
IEEE Transactions on Parallel and Distributed Systems
Consistency Analysis of Reconfigurable Dataflow Specifications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
PDP '96 Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96)
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient Computation of Buffer Capacities for Cyclo-Static Real-Time Systems with Back-Pressure
RTAS '07 Proceedings of the 13th IEEE Real Time and Embedded Technology and Applications Symposium
Modelling run-time arbitration by latency-rate servers in dataflow graphs
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Efficient computation of buffer capacities for cyclo-static dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Complex task activation schemes in system level performance analysis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs
IEEE Transactions on Computers
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
IEEE Transactions on Signal Processing
Parameterized dataflow modeling for DSP systems
IEEE Transactions on Signal Processing
Hierarchical finite state machines with multiple concurrency models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case throughput analysis of real-time dynamic streaming applications
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automatic dataflow model extraction from modal real-time stream processing applications
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
BPDF: a statically analyzable DataFlow model with integer and Boolean parameters
Proceedings of the Eleventh ACM International Conference on Embedded Software
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Increasingly, stream-processing applications include complex control structures to better adapt to changing conditions in their environment. This adaptivity often results in task execution rates that are dependent on the processed stream. Current approaches to compute buffer capacities that are sufficient to satisfy a throughput constraint have limited applicability in case of data-dependent task execution rates. In this article, we present a dataflow model that allows tasks to have loops with an unbounded number of iterations. For instances of this dataflow model, we present efficient checks on their validity. Furthermore, we present an efficient algorithm to compute buffer capacities that are sufficient to satisfy a throughput constraint. This allows to guarantee satisfaction of a throughput constraint over different modes of a stream processing application, such as the synchronization and synchronized modes of a digital radio receiver.