Consistency Analysis of Reconfigurable Dataflow Specifications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Consistency analysis of reconfigurable dataflow specifications
Embedded processor design challenges
Phased scheduling of stream programs
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Analysis of Dataflow Programs with Interval-limited Data-rates
Journal of VLSI Signal Processing Systems
Proceedings of the conference on Design, automation and test in Europe
Buffer capacity computation for throughput-constrained modal task graphs
ACM Transactions on Embedded Computing Systems (TECS)
BPDF: a statically analyzable DataFlow model with integer and Boolean parameters
Proceedings of the Eleventh ACM International Conference on Embedded Software
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Abstract: We present cyclo dynamic data flow (CDDF), a new data flow model for real time digital signal processing (DSP) applications. CDDF is an extension of cyclo static dataflow (CSDF) (G. Bilsen et al.; M. Engels et al., 1994) that keeps the interesting properties like analyzability and efficient compile time scheduling, while introducing data dependent control flow to improve the expressivity. The semantics are constructed such that extra knowledge about the internals of the actors, which is known to the programmer, can be expressed both in a natural way, and in a syntax that can be analyzed by automatic tools. We describe the proposed model in the context of already existing data flow languages, demonstrate its schedulability and its improved analyzability as compared to the Boolean data flow model (J.T. Buck, 1993).