Bandwidth scheduling for wide-area ATM networks using virtual finishing times
IEEE/ACM Transactions on Networking (TON)
Determining end-to-end delay bounds in heterogeneous networks
Multimedia Systems - Special issue on the fifth workshop on network and operating system support for digital audio and video 1995 (NOSSDAV)
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Performance bonds for flow control protocols
IEEE/ACM Transactions on Networking (TON)
Scheduling Parallel Computations
Journal of the ACM (JACM)
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Relationship between guaranteed rate server and latency rate server
Computer Networks: The International Journal of Computer and Telecommunications Networking
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Efficient Computation of Buffer Capacities for Cyclo-Static Real-Time Systems with Back-Pressure
RTAS '07 Proceedings of the 13th IEEE Real Time and Embedded Technology and Applications Symposium
IEEE Transactions on Signal Processing
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Monotonicity and run-time scheduling
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Dataflow models for shared memory access latency analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Buffer capacity computation for throughput-constrained modal task graphs
ACM Transactions on Embedded Computing Systems (TECS)
A new data flow analysis model for TDM
Proceedings of the tenth ACM international conference on Embedded software
Dataflow analysis for multiprocessor systems with non-starvation-free schedulers
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Flexible filters in stream programs
ACM Transactions on Embedded Computing Systems (TECS)
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In order to obtain a cost-efficient solution, tasks share resources in a Multi-Processor System-on-Chip. In our architecture, shared resources are run-time scheduled. We show how the effects of Latency-Rate servers, which is a class of run-time schedulers, can be included in a dataflow model. The resulting dataflow model, which can have an arbitrary topology, enables us to provide guarantees on the temporal behaviour of the implementation. Traditionally, the end-to-end behaviour of multiple Latency-Rate servers has been analysed with Latency-Rate analysis, which is a Network Calculus. This paper bridges a gap between Network Calculi and dataflow analysis techniques, since we show that a class of run-time schedulers can now be included in dataflow models, or, from a Network Calculus perspective, that restrictions on the topology of graphs that include run-time scheduling can be removed.