A Multiframe Model for Real-Time Tasks
IEEE Transactions on Software Engineering
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications
Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications
Performance Analysis of Real-Time Embeded Software
Performance Analysis of Real-Time Embeded Software
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Resource Reservation in Dynamic Real-Time Systems
Real-Time Systems
Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design Space Exploration and System Optimization with SymTA/S " Symbolic Timing Analysis for Systems
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Modelling run-time arbitration by latency-rate servers in dataflow graphs
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Efficient computation of buffer capacities for cyclo-static dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Complex task activation schemes in system level performance analysis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Implementing Synchronous Models on Loosely Time Triggered Architectures
IEEE Transactions on Computers
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
A Priority-Based Budget Scheduler with Conservative Dataflow Model
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Flow regulation for on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Signal Processing
Simultaneous budget and buffer size computation for throughput-constrained task graphs
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and analyzing real-time multiprocessor systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
The earlier the better: a theory of timed actor interfaces
Proceedings of the 14th international conference on Hybrid systems: computation and control
Compositional temporal analysis model for incremental hard real-time system design
Proceedings of the tenth ACM international conference on Embedded software
Analytical approaches for performance evaluation of networks-on-chip
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Dynamic scheduling of stream programs on embedded multi-core processors
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Dataflow analysis for multiprocessor systems with non-starvation-free schedulers
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
Automatic dataflow model extraction from modal real-time stream processing applications
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Modeling static-order schedules in synchronous dataflow graphs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Modern embedded multi-processors can execute several stream-processing applications concurrently. Typically, these applications are partitioned into tasks that communicate over buffers together forming a task graph. The fact that these applications are started and stopped by the user combined with the knowledge that not all applications are necessarily completely characterised makes it attractive to use run-time scheduling. We define and characterise a class of budget schedulers that by construction bound the interference from other applications. Furthermore, we will show that the worst-case effects of these schedulers can be included in dataflow process networks. The execution of the resulting dataflow process network is shown to result in tight and conservative bounds on the end-to-end temporal behaviour of the execution of the task graph on a cycle-true simulator. Given that the inter-task synchronisation of the application allows for a dataflow model that is functionally deterministic, this enables exploration of various buffer capacities and scheduler settings at a high level of abstraction.