Compositional temporal analysis model for incremental hard real-time system design

  • Authors:

  • Joost P.H.M. Hausmans;Stefan J. Geuns;Maarten H. Wiggers;Marco J.G. Bekooij

  • Affiliations:

  • University of Twente, Enschede, Netherlands;University of Twente, Enschede, Netherlands;Fujitsu Laboratories of America, Sunnyvale, CA, USA;NXP Semiconductors, Eindhoven & University of Twente, Enschede, Netherlands

  • Venue:
  • Proceedings of the tenth ACM international conference on Embedded software
  • Year:
  • 2012

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Abstract

The incremental design and analysis of parallel hard real-time stream processing applications is hampered by the lack of an intuitive compositional temporal analysis model that supports arbitrary cyclic dependencies between tasks. This paper introduces a temporal analysis model for hard real-time systems, called the Compositional Temporal Analysis (CTA) model, in which arbitrary cyclic dependencies can be specified. The CTA model also supports hierarchical composition and incremental design of timed components. The internals of a component in the CTA model can be hidden without changing the temporal properties of the component. Furthermore, the composition operation in the CTA model is associative, which enables composing components in an arbitrary order. Besides all these properties, also latency constraints and periodic sources and sinks can be specified and analyzed. We also show in this paper that for the CTA model efficient algorithms exist for buffer sizing, verifying consistency of compositions and to compute the temporal properties of compositions. The CTA model can be used as an abstraction of timed dataflow models. The CTA model uses components with transfer rates per port, in contrast to dataflow models that use actors with firing rules. Unlike dataflow models, the CTA model is not executable. An audio echo cancellation application is used to illustrate the applicability of the CTA model for a stream processing application with throughput and latency constraints, and to illustrate incremental design.