SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model

Authors:
Zhiliang Qian;Da-Cheng Juan;Paul Bogdan;Chi-Ying Tsui;Diana Marculescu;Radu Marculescu
Affiliations:
Hong Kong University of Science and Technology, Hong Kong;Carnegie Mellon University, Pittsburgh;Carnegie Mellon University, Pittsburgh and University of Southern California, Los Angeles;Hong Kong University of Science and Technology, Hong Kong;Carnegie Mellon University, Pittsburgh;Carnegie Mellon University, Pittsburgh
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 6
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Abstract

In this work, we propose SVR-NoC, a learning-based support vector regression (SVR) model for evaluating Network-on-Chip (NoC) latency performance. Different from the state-of-the-art NoC analytical model, which uses classical queuing theory to directly compute the average channel waiting time, the proposed SVR-NoC model performs NoC latency analysis based on learning the typical training data. More specifically, we develop a systematic machine-learning framework that uses the kernel-based support vector regression method to predict the channel average waiting time and the traffic flow latency. Experimental results show that SVR-NoC can predict the average packet latency accurately while achieving about 120X speed-up over simulation-based evaluation methods.