On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Analysis, modeling and generation of self-similar VBR video traffic
SIGCOMM '94 Proceedings of the conference on Communications architectures, protocols and applications
Fast, approximate synthesis of fractional Gaussian noise for generating self-similar network traffic
ACM SIGCOMM Computer Communication Review
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
Wavelet and rescaled range approach for the Hurst coefficient for short and long time series
Computers & Geosciences
Computer Networks: The International Journal of Computer and Telecommunications Networking - Special issue: Long range dependent trafic
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present the systolic architecture unit in NoC and address the fundamental issue of traffic modelling for systolic architectures unit in SoC design. We improve the synthetic trace generation method in order to simulate in systolic architectures unit and analyse the effect of the systolic architecture for traffic model, give the function HY=FHX1,HX2 by simulating and surface fitting for 2-input and 1-output systolic architecture unit traffic model. Our proposed technique allows designers implementing on-chip communication networks to model the traffic of any application by systolic architectures unit more effectively. This will enable systems designers to optimally their mapping and routing, architectures, and so on. Ultimately, designers will achieve optimal trade-off performance metrics and application quality.