ERA: an efficient routing algorithm for power, throughput and latency in network-on-chips

Authors:
Varsha Sharma;Rekha Agarwal;Manoj S. Gaur;Vijay Laxmi;Vineetha V.
Affiliations:
Computer Engineering Department, Malaviya National Institute of Technology, Jaipur, India;Computer Engineering Department, Malaviya National Institute of Technology, Jaipur, India;Computer Engineering Department, Malaviya National Institute of Technology, Jaipur, India;Computer Engineering Department, Malaviya National Institute of Technology, Jaipur, India;Computer Engineering Department, Malaviya National Institute of Technology, Jaipur, India
Venue:
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Year:
2010

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Abstract

Network-on-Chip (NoC) is viewed as a viable substitution for traditional interconnection networks to achieve high performance, communication efficiency and reliability in complex VLSI architectures at deep sub micron. Achieving high performance, power efficiency with optimum area is a target for any routing algorithm in NoC. In this paper, we propose a novel routing scheme named 'ERA', which offers higher throughput with controlled delays while remaining power aware. ERA is an adaptive routing algorithm, which avoids congestion and tends to minimize the hot spots in the network. Unlike other existing algorithms, the proposed algorithm does not require any virtual channels to avoid deadlocks. We compare our algorithm with XY and OE on the basis of a performance metric called 'power performance factor' for different traffic patterns and injection models. Our results show that ERA performs better than these two algorithms.