Motion Field and Optical Flow: Qualitative Properties
IEEE Transactions on Pattern Analysis and Machine Intelligence
Performance of optical flow techniques
International Journal of Computer Vision
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Electronic digital image stabilization: design and evaluation, with applications
Electronic digital image stabilization: design and evaluation, with applications
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Parallel Computers Two: Architecture, Programming and Algorithms
Parallel Computers Two: Architecture, Programming and Algorithms
Shooting a smooth video with a shaky camera
Machine Vision and Applications
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
The evaluation of normalized cross correlations for defect detection
Pattern Recognition Letters
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
SIMD, SMP and MIMD-DM Parallel Approaches for Real-Time 2D Image Stabilization
CAMP '05 Proceedings of the Seventh International Workshop on Computer Architecture for Machine Perception
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
HICSS '06 Proceedings of the 39th Annual Hawaii International Conference on System Sciences
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Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.