On-line fault detection for bus-based field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Efficient on-line testing of FPGAs with provable diagnosabilities
Proceedings of the 41st annual Design Automation Conference
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
NOC-centric Security of Reconfigurable SoC
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Examining the viability of FPGA supercomputing
EURASIP Journal on Embedded Systems
Toward Increasing FPGA Lifetime
IEEE Transactions on Dependable and Secure Computing
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Modeling reconfiguration in a FPGA with a hardwired network on chip
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modern Field Programmable Gate Arrays (FPGAs) posses small feature sizes, and have gained popularity in mission-critical systems. However, FPGA can suffer from faults due to the small feature sizes and harsh external conditions that are faced by a mission-critical system. Therefore, the architecture of FPGA must be tested to ensure a reliable system performance. At the same time, due to the mission-critical nature of a system, the test process should be non-intrusive, i.e., applications and FPGA regions that are not being tested remain unaffected. An online test methodology is, therefore, required that not only verifies the reliability of FPGA architecture, but also does not degrade the performance of other, running FPGA applications. In this paper, we propose an online test methodology that uses hardwired network on chip as test access mechanism, and conducts test on a region-wise basis. Importantly, the proposed test methodology exhibits a non-intrusive behaviour that means it does not affect the applications and FPGA regions, which are not being tested, in terms of configuration, programming, and execution. Our test methodology posses approx. 32 times lower fault detection latency as compared to existing schemes, respectively.