HAGAR: Efficient Multi-context Graph Processors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Hardware-Assisted Fast Routing
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Online resource management in a multiprocessor with a network-on-chip
Proceedings of the 2007 ACM symposium on Applied computing
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
An energy and performance exploration of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
Run-time spatial resource management for real-time applications on heterogeneous MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Time-division-multiplexed networks based on the contention-free routing model represent an attractive high-performance and low-cost solution for on-chip communication thanks to their low buffer requirements at the router level. Traditionally, allocating the slots for each connection in the network TDM tables was performed at design time, thus requiring prior knowledge of the application communication demands and as a consequence making this approach unfeasible to certain classes of problems. In this paper we propose performing the slot allocation on demand, at run time. While this approach is not new, we improve upon the state-of-the-art in terms of speed by more than one order of magnitude, while at the same time requiring less memory space.