An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing

Authors:
Ming Li;Wen-Ben Jone;Qing-An Zeng
Affiliations:
University of Cincinnati, Cincinnati OH;University of Cincinnati, Cincinnati OH;University of Cincinnati, Cincinnati OH
Venue:
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Year:
2006

Citing 0
Cited 2

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Test pin count reduction for NoC-based test delivery in multicore SOCs

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

This paper presents a floorplanning method based on particle swarm optimization (PSO). We adopted the B*-tree floorplan structure to generate an initial stage with overlap free for placement and utilized PSO to find out the potential optimal placement ...