Introduction to Algorithms
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC
Proceedings of the 49th Annual Design Automation Conference
A spectral clustering approach to application-specific network-on-chip synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
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Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.