Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Reducing power density through activity migration
Proceedings of the 2003 international symposium on Low power electronics and design
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Distributing the Frontend for Temperature Reduction
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Temperature-Sensitive Loop Parallelization for Chip Multiprocessors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Compiler-driven register re-assignment for register file power-density and temperature reduction
Proceedings of the 45th annual Design Automation Conference
Temperature-aware register reallocation for register file power-density minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Adapting application execution in CMPs using helper threads
Journal of Parallel and Distributed Computing
Thermal-aware compilation for system-on-chip processing architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
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As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance improvements. While high power consumption brings many problems with it, high power density and thermal hotspots are maybe two of the most important ones. Current architectures provide several circuit based solutions to cope with thermal emergencies when they occur but exercising them frequently can lead to significant performance losses. This paper proposes a compiler-based approach that balances the computational workload across the processors of an NoC based chip multiprocessor such that the chances of experiencing a thermal emergency at runtime are reduced. Our results show that the proposed approach cuts the number of runtime thermal emergencies by 42% on the average on benchmarks tested.