Temperature-Sensitive Loop Parallelization for Chip Multiprocessors

Authors:
Sri Hari Krishna Narayanan;Guilin Chen;Mahmut x. Mahmut Kandemir;Yuan Xie
Affiliations:
Department of CSE, The Pennsylvania State University;Department of CSE, The Pennsylvania State University;Department of CSE, The Pennsylvania State University;Department of CSE, The Pennsylvania State University
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9 degree C (4.3 degree C) when averaged over all the applications tested, incurring small performance/power penalties.