The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Rent's rule and parallel programs: characterizing network traffic behavior
Proceedings of the 2008 international workshop on System level interconnect prediction
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
The 48-core SCC Processor: the Programmer's View
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
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This paper focuses on the network on chip of multi-core systems and proposes empirical and theoretical lower bounds on the energy consumption of applications. The empirical method consists of an linear programming model that simultaneously reduces communication distances and network traffic. When applied to standard benchmarks, our method shows that locality exploitation can lead to 50% energy reduction on average compared to no optimization. The theoretical lower bound is based on the Rent's rule model from VLSI design, and is obtained analytically from the communication graph structure of applications. The theoretical results show excellent agreement with the empirical lower bound.