The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Proceedings of the 6th international workshop on Hardware/software codesign
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fractal communication in software data dependency graphs
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
Flow-aware allocation for on-chip networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Hybrid network on chip (HNoC): local buses with a global mesh architecture
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
An optimized multicore cache coherence design for exploiting communication locality
Proceedings of the great lakes symposium on VLSI
Implications of electronics technology trends to algorithm design
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
Handling global traffic in future CMP NoCs
Proceedings of the International Workshop on System Level Interconnect Prediction
Empirical and theoretical lower bounds on energy consumption for networks on chip
Proceedings of the Sixth International Workshop on Network on Chip Architectures
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In VLSI systems, Rent's rule characterizes the locality of interconnect between different subsystems, and allows an efficient layout of the circuit on a chip. With rising complexities of both hardware and software, Systems-on-Chip are converging to multiprocessor architectures connected by a Network-on-Chip. Here, packets are routed instead of wires, and threads of a parallel program are distributed among processors. Still, Rent's rule remains applicable, as it can now be used to describe the locality of network traffic. In this paper, we analyze network traffic on an on-chip network and observe the power-law relation between the size of clusters of network nodes and their external bandwidths. We then use the same techniques to study the time-varying behavior of the application, and derive the implications for future on-chip networks.