Realization of video object plane decoder on on-chip network architecture

Authors:
Huy-Nam Nguyen;Vu-Duc Ngo;Hae-Wook Choi
Affiliations:
System VLSI Lab Laboratory, SITI Research Center, School of Engineering, Information and Communications University (ICU), Yusong, Taejon, Korea;System VLSI Lab Laboratory, SITI Research Center, School of Engineering, Information and Communications University (ICU), Yusong, Taejon, Korea;System VLSI Lab Laboratory, SITI Research Center, School of Engineering, Information and Communications University (ICU), Yusong, Taejon, Korea
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

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Abstract

System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired bus-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. In this paper, we present interconnected network topologies and analyze their performances with a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Fat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.