Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Multi-Objective Optimization Using Evolutionary Algorithms
Multi-Objective Optimization Using Evolutionary Algorithms
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Towards efficient design space exploration of heterogeneous embedded media systems
Embedded processor design challenges
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
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Network on Chip (NoC) is a new paradigm for design core based System on Chip (SoC) which supports high degree of reusability and provides increase computation power. This paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a mesh-based NoC in two systematic steps using multi-objective evolutionary algorithm. The main objective is to obtain the pareto mappings that minimized the energy consumption (computational and communicational) and link bandwidth requirement under performance constraints. The evaluation performed on three randomly generated benchmarks and a real application (M-JPEG encoder) to conform the efficiency, accuracy and scalability of the proposed approach. Our proposed approach saves up to 15--20% of energy and bandwidth requirements compared with the existing approaches.