Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs

Authors:
Andrew G. Schmidt;Bin Huang;Ron Sass;Matthew French
Affiliations:
-;-;-;-
Venue:
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Year:
2011

Citing 0
Cited 2

An evaluation of an integrated on-chip/off-chip network for high-performance reconfigurable computing

International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
HwPMI: an extensible performance monitoring infrastructure for improving hardware design and productivity on FPGAs

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)

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Abstract

As FPGA resources continue to increase, FPGAs present attractive features to the High Performance Computing community. These include the power-efficient computation and application-specific acceleration benefits, as well as tighter integration between compute and I/O resources. This paper considers the ability of an FPGA to address another, increasingly important, feature -- resiliency. Specifically, a minimally-invasive monitoring infrastructure operating over a sideband network is presented. This includes a multi-chip protocol, IP cores that implement the protocol, and a tool to instrument existing hardware accelerator FPGA designs. To demonstrate the functionality, the system has been implemented on a cluster of FPGA devices running off-the-shelf MPI and Linux. We demonstrate the ability to do integrated software and hardware accelerator check pointing with restart under a variety of injected faults.