Low-complex dynamic programming algorithm for hardware/software partitioning

Authors:
Jigang Wu;Thambipillai Srikanthan
Affiliations:
School of Computer Engineering, Nanyang Technological University, Singapore 639798;School of Computer Engineering, Nanyang Technological University, Singapore 639798
Venue:
Information Processing Letters
Year:
2006

Citing 12
Cited 4

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FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
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EDTC '96 Proceedings of the 1996 European conference on Design and Test
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning

CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Communication Scheduling Algorithm for Multi-FPGA Systems

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Preference-Driven Hierarchical Hardware/Software Partitioning

ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design

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Mathematical and Computer Modelling: An International Journal
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ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
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Journal of Systems Architecture: the EUROMICRO Journal
Efficient heuristic and tabu search for hardware/software partitioning

The Journal of Supercomputing

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Abstract

A low-complex algorithm is proposed for the hardware/software partitioning. The proposed algorithm employs dynamic programming principles while accounting for communication delays. It is shown that the time complexity of the latest algorithm has been reduced from O(n^2@?A) to O(n@?A), without increase in space complexity, for n code fragments and hardware area A.