Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
EURO-DAC '94 Proceedings of the conference on European design automation
Clustering for improved system-level functional partitioning
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A path analysis based partitioning for time constrained embedded systems
Proceedings of the 6th international workshop on Hardware/software codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Integer Programming for Partitioning in Software Oriented Codesign
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Communication Scheduling Algorithm for Multi-FPGA Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Preference-Driven Hierarchical Hardware/Software Partitioning
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
New model and algorithm for hardware/software partitioning
Journal of Computer Science and Technology
Robust Software Partitioning with Multiple Instantiation
INFORMS Journal on Computing
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A low-complex algorithm is proposed for the hardware/software partitioning. The proposed algorithm employs dynamic programming principles while accounting for communication delays. It is shown that the time complexity of the latest algorithm has been reduced from O(n2 ċ A) to O(n ċ A), without increase in space complexity, for n code fragments and hardware area A.