New model and algorithm for hardware/software partitioning

Authors:
Ji-Gang Wu;Thambipillai Srikanthan;Guang-Wei Zou
Affiliations:
Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore
Venue:
Journal of Computer Science and Technology
Year:
2008

Citing 14
Cited 1

Synthesis and simulation of digital systems containing interacting hardware and software components

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning

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Clustering for improved system-level functional partitioning

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Hardware/software partitioning with integrated hardware design space exploration

Proceedings of the conference on Design, automation and test in Europe
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware-Software partitioning and pipelined scheduling of transformative applications

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Hardware-Software Cosynthesis for Digital Systems

IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers

IEEE Design & Test
Integer Programming for Partitioning in Software Oriented Codesign

FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
On the hardware-software partitioning problem: System modeling and partitioning techniques

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware/Software Partitioning using Integer Programming

EDTC '96 Proceedings of the 1996 European conference on Design and Test
Preference-Driven Hierarchical Hardware/Software Partitioning

ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Algorithmic aspects of hardware/software partitioning

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-complex dynamic programming algorithm for hardware/software partitioning

Information Processing Letters

Efficient heuristic algorithms for path-based hardware/software partitioning

Mathematical and Computer Modelling: An International Journal

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Abstract

This paper focuses on the algorithmic aspects for the hardware/software (HW/SW) partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O(n ċ A) for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.