Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures

Authors:
Vinoo Srinivasan;Ranga Vemuri
Affiliations:
-;-
Venue:
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
1999

Citing 1
Cited 1

Hierarchical behavioral partitioning for multicomponent synthesis

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Automated design synthesis and partitioning for adaptive reconfigurable hardware

Hardware implementation of intelligent systems

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Abstract

This paper presents spade , a system for partitioning designs onto multi- fpga architectures. The input to spade is a task graph, that is composed of computational tasks, memory tasks and the communication and synchronization between tasks. spade consists of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization and rtl design space exploration heuristic. We show how various architectural constraints can be effectively handled using an iterative partitioning engine.